Field of the Invention
The present invention relates generally to systems and methods for performing model-based scanner tuning and optimization and more particularly to optimization of performance of multiple lithography systems.
Description of Related Art
Lithographic apparatus can be used in the manufacture of integrated circuits (ICs). A mask contains a circuit pattern corresponding to an individual layer of the IC, and this pattern is imaged onto a target portion comprising one or more dies on a substrate of silicon wafer that has been coated with a layer of radiation-sensitive resist material. In general, a single wafer will contain a network of adjacent target portions that are successively irradiated via the projection system, one at a time. In one type of lithographic projection apparatus, commonly referred to as a wafer stepper, each target portion is irradiated by exposing the entire mask pattern onto the target portion in one pass. In s step and scan apparatus, each target portion is irradiated by progressively scanning the mask pattern under the projection beam in a given reference or “scanning direction” while synchronously scanning the substrate table parallel or anti parallel to this direction. In a projection system having a magnification factor M (generally <1), the speed Vat which the substrate table is scanned will be a factor M times that at which the mask table is scanned. More information with regard to lithographic devices as described herein can be gleaned, for example, from U.S. Pat. No. 6,046,792, incorporated herein by reference.
In a manufacturing process using a lithographic projection apparatus, a mask pattern is imaged onto a substrate that is at least partially covered by a layer of radiation sensitive resist material. Prior to this imaging step, the substrate may undergo various procedures, such as priming, resist coating and soft bake. After exposure, the substrate may be subjected to other procedures, such as a post exposure bake (PEB), development, a hard bake and measurement/inspection of the imaged features. This array of procedures is used as a basis to pattern an individual layer of a device, e.g., an IC. Such a patterned layer may then undergo various processes such as etching, ion implantation or doping, metallization, oxidation, chemo mechanical polishing, etc. to finish an individual layer. If several layers are required, then the procedure, or a variant thereof, will have to be repeated for each new layer. Eventually, an array of devices will be present on the substrate wafer. These devices are then separated from one another by a technique such as dicing or sawing and the individual devices can be mounted on a carrier, connected to pins, etc.
A projection system (hereinafter the “lens”) encompasses various types of projection systems, including, for example refractive optics, reflective optics, and catadioptric systems and may include one or more lens. The lens may also include components of a radiation system used for directing, shaping or controlling the projection beam of radiation. Further, the lithographic apparatus may be of a type having two or more substrate tables and/or two or more mask tables. In such multiple stage devices the additional tables may be used in parallel and/or preparatory steps may be carried out certain tables while other tables are used for exposure. Twin stage lithographic apparatus are described, for example, in U.S. Pat. No. 5,969,441, incorporated herein by reference.
The photolithographic masks referred to above comprise geometric patterns corresponding to the circuit components to be integrated onto a silicon wafer. The patterns used to create such masks are generated utilizing computer-aided design (“CAD”) programs, this process often being referred to as electronic design automation (“EDA”). Most CAD programs follow a set of predetermined design rules in order to create functional masks. These rules are set by processing and design limitations. For example, design rules define the space tolerance between circuit devices such as gates, capacitors, etc. or interconnect lines, so as to ensure that the circuit devices or lines do not interact with one another in an undesirable way. The design rule limitations are typically referred to as critical dimensions (“CDs”). A CD of a circuit can be defined as the smallest width of a line or hole or the smallest space between two lines or two holes. Thus, the CD determines the overall size and density of the designed circuit. Of course, one of the goals in integrated circuit fabrication is to faithfully reproduce the original circuit design on the wafer via the mask.
Generally, benefit may accrue from utilizing a common process for imaging a given pattern with different types of lithography systems, such as scanners, without having to expend considerable amounts of time and resources determining the necessary settings of each lithography system to achieve optimal/acceptable imaging performance. Designers and engineers can spend a considerable amount of time and money determining optimal settings of a lithography system which include numerical aperture (“NA”), σin, σout, etc., when initially setting up a process for a particular scanner and to obtain images that satisfy predefined design requirements. Often, a trial and error process is employed wherein the scanner settings are selected and the desired patterns are imaged and then measured to determine if the output images fall within specified tolerances. If the output images are out of tolerance, the scanner settings are adjusted and the patterns are imaged once again and measured. This process is repeated until the resulting images are within the specified tolerances.
However, an actual pattern imaged on a substrate can vary from scanner to scanner due to the different optical proximity effects (“OPEs”) exhibited by different scanners when imaging a pattern, even when the scanners are of identical model types. For example, different OPEs associated with certain scanners can introduce significant CD variations through pitch. Consequently, it is often impossible to switch between scanners and obtain identical imaged patterns. Thus, engineers must optimize or tune a scanner when that scanner is new or different and is to be used to print a pattern with the expectation of obtaining resulting images that satisfy the design requirements. Currently, an expensive, time-consuming trial and error process is used to adjust processes and scanners.
In the current state of the art, a common form of scanner tuning is proximity matching. The goal is to match printed wafer CDs for a set of predefined patterns between a tunable scanner and a reference scanner. Typically the emphasis is on one dimensional patterns (“1D patterns”) through pitch, as the critical dimension uniformity for those patterns is most critical for semiconductor device performance. The predefined patterns are exposed on wafer using the reference scanner and the tunable scanner, and wafer CD values are measured. The differences in CD are used to drive tuning offsets on the tunable scanner, in order to match the CD values after tuning to those from the reference scanner. Optimization is performed in a linear fashion, assuming a linear dependency of CD values relative to tuning offsets. The linear dependency is characterized by sensitivities, defined as partial derivatives of CD values to knob offsets. The sensitivities may be measured or simulated from a lithography model, such as one provided by U.S. Pat. No. 7,003,758.
There are a few shortcomings of the existing methodology, which the current invention seeks to overcome. First, every pattern to be matched must be measured, which is not the most efficient use of the wafer metrology time in the fab (usually in high demand). Conversely, there is no claim to the level of matching or imaging behavior for patterns other than those measured. This is known to have caused problems in production environments, where a set of 1D patterns are matched sufficiently well, but some two-dimensional (“2D”) real device patterns had demonstrably mismatched results in the wafer imaging after tuning. See, “Accurate Model Base Verification Scheme To Eliminate Hotspots And Manage Warmspots,” Proc. SPIE, Vol. 6925, 69250Z (2008) and “Scanner Fleet Management Utilizing Programmed Hotspot Patterns,” Proc. SPIE, Vol. 7028, 70280W (2008).